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ADE7518
OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0, normal operating mode, V SWOUT is connected to V DD .
All of the analog circuitry and digital circuitry powered by
V INTD and V INTA are enabled by default. In normal mode, the
default clock frequency, f CORE , established during a power-on
PSM2 (SLEEP MODE)
PSM2 is a low power consumption sleep mode for use in battery
operation. In this mode, V SWOUT is connected to V BAT . All of the
2.5 V digital and analog circuitry powered through V INTA and V INTD
are disabled, including the MCU core, resulting in the following:
reset or software reset, is 1.024 MHz.
PSM1 (BATTERY MODE)
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The RAM in the MCU is no longer valid.
The program counter for the 8052, also held in volatile
In PSM1, battery mode, V SWOUT is connected to V BAT . In this
operating mode, the 8052 core and all of the digital circuitry are
enabled by default. The analog circuitry for the ADE energy
metering DSP powered by V INTA is disabled. This analog circuitry
automatically restarts, and the switch to the V DD power supply
occurs when the V DD supply is above 2.75 V and the PWRDN
bit in the MODE1 register (0x0B) is cleared (see Table 31). The
default f CORE for PSM1, established during a power-on reset or
software reset, is 1.024 MHz.
memory, becomes invalid when the 2.5 V supply is shut
down. Therefore, the program does not resume from
where it left off but always starts from the power-on reset
vector when the ADE7518 exits PSM2.
The 3.3 V peripherals (RTC, and LCD) are active in PSM2.
They can be enabled or disabled to reduce power consumption
and are configured for PSM2 operation when the MCU core is
active (see Table 27 for more information about the individual
peripherals and their PSM2 configuration). The ADE7518
remains in PSM2 until an event occurs to wake them up.
In PSM2, the ADE7518 provides four scratch pad RAM SFRs
that are maintained during this mode. These SFRs can be used
to save data from PSM0 or PSM1 when entering PSM2 (see
Table 20 to Table 23).
In PSM2, the ADE7518 maintains some SFRs (see Table 26).
The SFRs that are not listed in this table should be restored
when the part enters PSM0 or PSM1 from PSM2.
Table 26. SFRs Maintained in PSM2
I/O Configuration
Interrupt Pins Configuration SFR
(INTPR, 0xFF), see Table 15
Peripheral Configuration SFR
(PERIPH, 0xF4), see Table 18
Power Supply Management
Battery Switchover Configuration
SFR (BATPR, 0xF5), see Table 17
RTC Peripherals
RTC Nominal Compensation SFR
(RTCCOMP, 0xF6), see Table 115
RTC Temperature Compensation
SFR (TEMPCAL, 0xF7),
LCD Peripherals
LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED), see Table 77
LCD Configuration Y SFR
(LCDCONY, 0xB1), see Table 70
see Table 116
Port 0 Weak Pull-Up Enable SFR
(PINMAP0, 0xB2), see Table 138
Port 1 Weak Pull-Up Enable SFR
(PINMAP1, 0xB3), see Table 139
Port 2 Weak Pull-Up Enable SFR
(PINMAP2, 0xB4), see Table 140
Scratch Pad 1 SFR
(SCRATCH1, 0xFB), see Table 20
Scratch Pad 2 SFR
(SCRATCH2, 0xFC), see Table 21
Scratch Pad 3 SFR
(SCRATCH3, 0xFD), see Table 22
RTC Configuration SFR
(TIMECON, 0xA1), see Table 109
Hundredths of a Second
Counter SFR
(HTHSEC, 0xA2), see Table 110
Seconds Counter SFR
(SEC, 0xA3), see Table 111
Minutes Counter SFR
(MIN, 0xA4), see Table 112
Hours Counter SFR
(HOUR, 0xA5), see Table 113
Alarm Interval SFR
(INTVAL, 0xA6), see Table 114
LCD Configuration X SFR
(LCDCONX, 0x9C), see Table 69
LCD Configuration SFR
(LCDCON, 0x95), see Table 68
LCD Clock SFR
(LCDCLK, 0x96), see Table 71
LCD Segment Enable SFR
(LCDSEGE, 0x97), see Table 74
LCD Pointer SFR
(LCDPTR, 0xAC), see Table 75
LCD Data SFR
(LCDDAT, 0xAE), see Table 76
Scratch Pad 4 SFR
(SCRATCH4, 0xFE), see Table 23
Rev. 0 | Page 30 of 128
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